Dynamic random access memory (DRAM) generally use a voltage supply of Vdd, or some other voltage proportional to Vdd, for precharge and equilibration of the bit lines prior to a read of the memory cell(s). In most current DRAM designs, the voltage supply used for precharge and equilibration is about one-half of Vdd (Vdd/2 supply). Use of the Vdd/2 supply has several advantages, including a reduction in peak currents at both sensing and bit-line precharge due to the half Vdd swing, and when folded bit lines are used, a reduction in noise coupling to the memory cell plate, the array substrate and word lines.
A typical DRAM cell includes a capacitor that stores a voltage level representing a logic zero or logic one. The other end of the capacitor is coupled to memory cell plate that runs throughout the memory array. The memory cell plate is typically biased at ground potential or some other voltage proportional to Vdd. In most current DRAM designs, the memory cell plate is coupled to a voltage supply equal to about one-half Vdd. The Vdd/2 bias on the memory cell plate has several advantages, including a reduction in the maximum voltage across the capacitor dielectric.
In a typical DRAM integrated circuit, virtually the entire integrated circuit is dedicated to the DRAM finction, including a relatively small amount of logic and peripheral circuitry used for I/O, selection and timing for the DRAM. Accordingly, the switching loads in a typical DRAM have less impact and relatively little noise is generated on the Vdd supply. Therefore, the Vdd power supply that provides the source for the VDD/2 supplies for the precharge/equilibration of the bit lines and the memory cell plate, is low in noise. In addition, some noise generated on the Vdd supply by operation of the DRAM is generally predictable and relatively stable, thus allowing designers to design its operation to reduce the effects of the noise. Given the low noise, a typical DRAM performs the sensing function substantially concurrently with the restore function. This provides a faster sensing operation.
When an integrated circuit includes substantial circuitry that performs many different and varying functions (e.g., processor, high-speed I/O, analog, etc.), the switching loads are high and random. Combining a DRAM into an application specific integrated circuit (ASIC), a processor-based integrated circuit, or as a relatively small portion of some other integrated circuit - commonly referred to as "embedded DRAM" presents many problems. One main problem is an increase in the amount of noise on the Vdd supply caused by the high switching loads. Another problem is the randomness of the switching loads (that is, the operation of the other circuitry on the IC may not be related to the operation of the DRAM on the IC). Due to this, it is very difficult to design the DRAM to reduce the effects of this noise. Moreover, the sensing of the bit lines in a DRAM is a very sensitive time.
Accordingly, there exists a need to reduce the noise in a DRAM in an integrated circuit. In addition, there is a need for a method and apparatus that reduces the effects of noise on a embedded DRAM.